View SAA7345GP_363889.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
DATA SHEET
SAA7345 CMOS digital decoding IC with RAM for Compact Disc
Product specification Supersedes data of 1996 Jan 09 File under Integrated Circuits, IC01 1998 Feb 16
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
FEATURES * Integrated data slicer and clock regenerator * Digital Phase-Locked Loop (PLL) * Demodulator and Eight-to-Fourteen Modulation (EFM) decoding * Subcoding microcontroller serial interface * Integrated programmable motor speed control * Error correction and concealment functions * Embedded Static Random Access Memory (SRAM) for de-interleave and First-In First-Out (FIFO) * FIFO overflow concealment for rotational shock resistance * Digital audio interface [European Broadcasting Union (EBU)] * 2 to 4 times oversampling integrated digital filter * Audio data peak level detection * Versatile audio data serial interface * Digital de-emphasis filter * Kill interface for Digital-to-Analog Converter (DAC) deactivation during digital silence * Double speed mode * Compact Disc Read Only Memory (CD-ROM) modes * A single speed only version is available (SAA7345GP/SS). QUICK REFERENCE DATA SYMBOL VDD IDD fxtal Tamb Tstg supply voltage supply current crystal frequency operating ambient temperature storage temperature PARAMETER 3.4 - 8 -40 -55 MIN. 5.0 22 16.9344 or 33.8688 - - TYP. 5.5 50 35 +85 +125 MAX. GENERAL DESCRIPTION
SAA7345
The SAA7345 incorporates the CD signal processing functions of decoding and digital filtering. The device is equipped with on-board SRAM and includes additional features to reduce the processing required in the analog domain. Supply of this Compact Disc IC does not convey an implied license under any patent right to use this IC in any Compact Disc application.
UNIT V mA MHz C C
ORDERING INFORMATION TYPE NUMBER SAA7345GP PACKAGE NAME QFP44 DESCRIPTION plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm VERSION SOT205-1
1998 Feb 16
2
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
BLOCK DIAGRAM
SAA7345
V DDA 11 HFIN HFREF ISLICE IREF TEST1 TEST2 CRIN CROUT CL11 CLA CL16 8 9 7 10 6 5 13 14 1 29 17 TIMING
VSSA 12 DIGITAL PLL
VDD1 15
VSS1 16
VDD2 44
VSS2 43 22 MOTO1 MOTO2
PLL FRONTEND SUBCODE EFM DEMODULATOR
MOTOR CONTROL
23
ERROR CORRECTOR FLAGS 33 CFLG
SRAM AUDIO PROCESSOR RAM ADDRESSER
SAA7345
EBU INTERFACE
2
DOBM
Q - CHANNEL CRC CHECK CL DA RAB 31 30 32 MICROCONTROLLER INTERFACE VERSATILE PINS INTERFACE 3 V1 4 V2 26 V3 25 V4 24 V5 KILL 27 KILL
MGA371 - 2
Q - CHANNEL REGISTER
PEAK DETECT
21 SERIAL DATA INTERFACE 20 19 18
SCLK WCLK DATA MISC
PORE
28
Fig.1 Block diagram.
1998 Feb 16
3
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
PINNING SYMBOL CL11 DOBM V1 V2 TEST2 TEST1 ISLICE HFIN HFREF IREF VDDA VSSA CRIN CROUT VDD1 VSS1 CL16 MISC DATA WCLK SCLK MOTO1 MOTO2 V5 V4 V3 KILL PORE CLA DA CL RAB CFLG n.c. VSS2 VDD2 Note 1. All supply pins must be connected to the same external power supply. PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 43 44 DESCRIPTION 11.2896 or 5.6448 MHz clock output (3-state); (divide-by-3) bi-phase mark output (externally buffered; 3-state) versatile input pin versatile input pin test input; this pin should be tied LOW test input; this pin should be tied LOW current feedback output from data slicer comparator signal input comparator common-mode input reference current pin (nominally 12VDD) analog supply voltage; note 1 analog ground; note 1 crystal/resonator input crystal/resonator output digital supply to input and output buffers; note 1 digital ground to input and output buffers; note 1 16.9344 MHz system clock output general purpose DAC output (3-state) serial data output (3-state) word clock output (3-state) serial bit clock output (3-state) motor output 1; versatile (3-state) motor output 2; versatile (3-state) versatile output pin versatile output pin versatile output pin (open-drain) kill output; programmable (open-drain) power-on reset enable input (active LOW) 4.2336 MHz microcontroller clock output interface data I/O line interface clock input line interface R/W and acknowledge input correction flag output (open-drain) digital ground to internal logic; note 1 digital supply voltage to internal logic; note 1
SAA7345
34 to 42 no internal connection
1998 Feb 16
4
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
SAA7345
44 V DD2
VSS2
Pins 34 to 42 (inclusive) have no internal connection 41 40 39 38 42 37 36 35 34
CL11 DOBM V1 V2 TEST2 TEST1 ISLICE HFIN HFREF
1 2 3 4 5 6 7 8 9
43
33 CFLG 32 RAB 31 CL 30 DA 29 CLA
SAA7345
28 PORE 27 KILL 26 V3 25 V4 24 V5 23 MOTO2
IREF 10 VDDA 11
WCLK 20
SCLK 21
MOTO1 22
V SSA 12
CRIN 13
CROUT 14
V DD1 15
VSS1 16
CL16 17
MISC 18
DATA 19
MGA359 - 1
Fig.2 Pin configuration.
1998 Feb 16
5
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
FUNCTIONAL DESCRIPTION Demodulator FRAME SYNC PROTECTION This circuit will detect the frame synchronization signals. Two synchronization counters are used in the SAA7345: 1. The coincidence counter which is used to detect the coincidence of successive syncs. It generates a Sync coincidence signal if 2 syncs are 588 1 EFM clocks apart. 2. The main counter is used to partition the EFM signal into 17-bit words. This counter is reset when: a) A Sync coincidence is generated. b) A sync is found within 6 EFM clocks of its expected position. The Sync coincidence signal is also used to generate the Lock signal which will go active HIGH when 1 Sync coincidence is found. It will reset to LOW when, during 61 consecutive frames, no Sync coincidence is found. This Lock signal is accessed via the status signal when the status control register (address 0010) is set to X100. See section on "Microcontroller interface" . Data Slicer and Clock Regenerator The SAA7345 has an integrated slice level comparator which is clocked by the crystal frequency clock. The slice level is controlled by an internal current source applied to an external capacitor under the control of the digital phase-locked loop (DPLL).
SAA7345
Regeneration of the bit clock is achieved with an internal fully digital PLL. No external components are required and the bit clock is not output. The PLL has two microcontroller control registers (addresses 1000 and 1001) for bandwidth and equalization. For certain applications an off-track input is necessary. If this flag is HIGH, the SAA7345 will assume that the servo is following on the wrong track, and will flag all incoming HF data as incorrect. The off-track is input via the V1 pin when the versatile pins interface register (address 1100) bit 0 is set to logic 1. EFM demodulation The 14-bit EFM data and subcode words are decoded into 8-bit symbols. Subcode data processing Q-CHANNEL PROCESSING The 96-bit Q-channel word is accumulated in an internal buffer. Sixteen bits are used to perform a Cyclic Redundancy Check (CRC). If the data is good, the SUBQREADY-I signal will go LOW. SUBQREADY-I can be read via the status signal when the status control register (address 0010) is set to X000 (normal reset condition). Good Q-channel data may be read via the microcontroller interface.
crystal clock 2.2 k 2.2 nF 47 pF HFREF 22 k 22 nF VSSA 100 nF VSSA ISLICE 100 A Iref 1/2VDD 100 A VSS VDD DPLL HFIN D Q
HF input
MGA368 - 1
Fig.3 Data slicer showing typical application components.
1998 Feb 16
6
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
OTHER SUBCODE CHANNELS Data of the other subcode channels (Q-to-W) may be read via the V4 pin if the versatile pins interface register (address 1101) is set to XX01. The format is similar to RS232. The subcode sync word is formed by a pause of 200 s minimum. Each subcode byte starts with a logic 1 followed by 7 bits (Q-to-W). The gap between bytes is variable between 11.3 s and 90 s. The subcode data is also available in the EBU output (DOBM) in a similar format. Microcontroller interface The SAA7345 has a 3-line microcontroller interface which is compatible with the digital servo IC TDA1301. WRITING DATA TO SAA7345 The SAA7345 has thirteen 4-bit programmable configuration registers as shown in Table 2. These can be written to via the microcontroller interface using the protocol shown in Fig.5.
SAA7345
Write operation sequence
* RAB is held LOW by the microcontroller to hold the SAA7345 DA pin at high-impedance. * Microcontroller data is clocked into the internal shift register on the LOW-to-HIGH clock transition CL. * Data D (3 : 0) is latched into the appropriate control register [address bits A (3 : 0)] on the LOW-to-HIGH transition of RAB with CL HIGH. * If more data is clocked into SAA7345 before the LOW-to-HIGH transition of RAB then only the last 8 bits are used. * If less data is clocked into SAA7345, unpredictable operation will result. * If the LOW-to-HIGH transition of RAB occurs with CL LOW, the command will be disregarded.
200 s min W96 1
11.3 s Q1 R1 S1 T1 U1 V1 W1
11.3 s min 90 s max 1 Q2
MGA369
Fig.4 Subcode format and timing at V4 pin.
RAB (microcontroller) CL (microcontroller) DA (microcontroller) DA (SAA7345) A3 A2 A1 A0 D3 D2 D1 D0
high impedance
MGA379 - 1
Fig.5 Microcontroller WRITE timing.
1998 Feb 16
7
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
WRITING DATA TO SAA7345; REPEAT MODE
SAA7345
The same command can be repeated several times (e.g. for fade function) by applying extra RAB pulses as shown in Fig.6.
RAB (microcontroller) CL (microcontroller) DA (microcontroller) DA (SAA7345) A3 A2 A1 A0 D3 D2 D1 D0
high impedance
MGA380 - 1
Note that CL must stay HIGH between RAB pulses.
Fig.6 Microcontroller WRITE timing; repeat mode.
READING STATUS INFORMATION FROM SAA7345 There are several internal status signals which can be made available on the DA line (Table 1). Table 1 Internal status signals. SIGNAL SUBQREADY-I MOTSTART1 MOTSTART2 MOTSTOP PLL Lock V1 V2 MOTOR-OV DESCRIPTION LOW if new subcode word is ready in Q-channel register. HIGH if motor is turning at 75% or more of nominal speed. HIGH if motor is turning at 50% or more of nominal speed. HIGH if motor is turning at 12% or less of nominal speed. HIGH if Sync coincidence signals are found. Follows input on V1 pin. Follows input on V2 pin. HIGH if the motor servo output stage saturates.
The status signal to be output is selected by status control register (address 0010). The timing for reading the status signal is shown in Fig.7.
Status read operation sequence
* Write appropriate data to register 0010 to select required status signal. * With RAB LOW; set CL LOW. * Set RAB HIGH; this will instruct the SAA7345 to output status signal on DA.
1998 Feb 16
8
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
SAA7345
RAB (microcontroller) CL (microcontroller) DA (microcontroller)
high impedance STATUS
MGA381 - 1
DA (SAA7345)
Fig.7 SAA7345 status READ timing.
READING Q-CHANNEL SUBCODE FROM SAA7345 To read Q-channel subcode from SAA7345, the SUBQREADY-I signal should be selected as status signal. The subcode read timing is shown in Fig.8.
Read subcode operation sequence
* Monitor SUBQREADY-I status signal. * When this signal is LOW, and up to 2.3 ms after its LOW-to-HIGH transition, it is permitted to read subcode. * Set CL LOW, SAA7345 will output first subcode bit (Q1). * After subcode read starts, the microcontroller may take as long as it wants to terminate read operation. * SAA7345 will output consecutive subcode bits after each HIGH-to-LOW transition of CL. * When enough subcode has been read (1 to 96 bits), stop reading by pulling RAB LOW.
RAB (microcontroller) CL (microcontroller) DA (SAA7345) STATUS CRC OK Q1 Q2 Q3 Qn-2 Qn-1 Qn
MGA382 - 1
Fig.8 SAA7345 Q-channel subcode READ timing.
PEAK DETECTOR OUTPUT In place of the CRC-bits (bits 81 to 96), the peak detector information is added to the Q-channel data. The peak information corresponds to the highest audio level (absolute value) and is measured on positive peaks. Only the most significant 8 bits of the peak level are given, in unsigned notation. Bits 81 to 88 contain the LEFT peak value (bit 88 = MSB) and bits 89 to 96 contain the RIGHT channel (bit 96 = MSB). Value is reset after reading Q-channel data.
1998 Feb 16
9
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
BEHAVIOUR OF THE SUBQREADY-I SIGNAL When the CRC of the Q-channel word is good, and no subcode is being read, the SUBQREADY-I signal will react as shown in Fig.9. When the CRC is good and subcode is being read, the timing in Fig.10 applies. If t1 (SUBQREADY-I LOW to end of subcode read) is below 2.6 ms, then t2 = 13.1 ms (i.e. the microcontroller can read all subcode frames if it completes the read operation within 2.6 ms after subcode ready). If this criterion is not met, it is only possible to guarantee that t3 will be below 26.2 ms (approximately). If subcode frames with failed CRCs are present, the t2 and t3 times will be increased by 13.1 ms for each defective subcode frame.
SAA7345
SHARING THE MICROCONTROLLER INTERFACE When the RAB pin is held LOW by the microcontroller, it is permitted to put any signal on the DA and CL lines (SAA7345 will set output DA to high-impedance). Under this circumstance these lines may be used for another purpose (e.g. TDA1301 microcontroller interface Data and Clock line, see Fig.11).
RAB (microcontroller) CL (microcontroller) DA (SAA7345) high impedance CRC OK CRC OK
10.8 ms 2.3 ms READ start allowed
15.4 ms
MGA373 - 1
Fig.9 SUBQREADY-I timing when no subcode is read.
t2 t1 RAB (microcontroller) CL (microcontroller) DA (SAA7345) Q1 Q2 Q3 Qn
MGA374 - 1
t3
Fig.10 SUBQREADY-I timing when subcode is being read.
1998 Feb 16
10
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
SAA7345
TDA1301 SIDA SICL SILD
SAA7345 DA CL RAB
MGA361 - 1
MICROCONTROLLER
I/O O O O
Fig.11 SAA7345 microcontroller interface application diagram.
Table 2 Command registers. The `INITIAL' column shows the power-on reset state REGISTER Fade and Attenuation ADDRESS 0000 DATA X000 X01X X001 X100 X101 Motor mode 0001 X000 X001 X010 X011 X100 X101 X 111 X110 1XXX 0XXX Status control 0010 X000 X001 X010 X011 X100 X101 X110 X 111 0XXX 1XXX Mute Attenuate Full Scale Step Down Step Up Motor off mode Motor brake mode 1 Motor brake mode 2 Motor start mode 1 Motor start mode 2 Motor jump mode Motor play mode Motor jump mode 1 anti-windup active anti-windup off status = SUBQREADY-I status = MOTSTART1 status = MOTSTART2 status = MOTSTOP status = PLL Lock status = V1 status = V2 status = MOTOR-OV L channel first at DAC (WCLK normal) R channel first at DAC (WCLK inverted) Reset Reset Reset Reset FUNCTION INITIAL Reset
1998 Feb 16
11
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
REGISTER DAC output ADDRESS 0011 DATA 1010 1011 110X 1111 1110 000X 0011 0010 010X 0111 0110 Motor gain 0100 X000 X001 X010 X011 X100 X101 X110 X 111 Motor bandwidth 0101 XX00 XX01 XX10 XX11 00XX 01XX 10XX Motor output configuration 0110 XX00 XX01 XX10 XX11 00XX 01XX 10XX 11XX I2S FUNCTION CD-ROM mode EIAJ; CD-ROM mode I2S; 4fs mode I2S; I2S; 2fs mode fs mode
SAA7345
INITIAL
Reset
EIAJ; 16-bit; 4fs EIAJ; 16-bit; 2fs EIAJ; 16-bit; fs EIAJ; 18-bit; 4fs EIAJ; 18-bit; 2fs EIAJ; 18-bit; fs Motor gain G = 3.2 Motor gain G = 4.0 Motor gain G = 6.4 Motor gain G = 8.0 Motor gain G = 12.8 Motor gain G = 16.0 Motor gain G = 25.6 Motor gain G = 32.0 Motor f4 = 0.5 Hz Motor f4 = 0.7 Hz Motor f4 = 1.4 Hz Motor f4 = 2.8 Hz Motor f3 = 0.85 Hz Motor f3 = 1.71 Hz Motor f3 = 3.42 Hz Motor power maximum 37% Motor power maximum 50% Motor power maximum 75% Motor power maximum 100% MOTO1, MOTO2 pins 3-state Motor Pulse Width Modulation (PWM) mode Motor Pulse Density Modulation (PDM) mode Motor Compact Disc Video (CDV) mode Reset Reset Reset Reset Reset
1998 Feb 16
12
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
REGISTER ADDRESS DATA Loop BW (Hz) PLL loop filter bandwidth 1000 0000 0001 0010 0100 0101 0110 1000 1001 1010 1100 1101 1110 PLL loop filter equalization 1001 0001 0010 0011 0100 0101 EBU output 1010 XX00 XX10 XX11 X0XX X1XX 0XXX 1XXX Speed control 1011 1XXX 0XXX X0XX X1XX XX00 XX10 XX11 Versatile pins interface 1100 XXX1 XXX0 XX0X X01X X11X 1640 3279 6560 1640 3279 6560 1640 3279 6560 1640 3279 6560 FUNCTION Internal BW (Hz) 525 263 131 1050 525 263 2101 1050 525 4200 2101 1050
SAA7345
INITIAL Low-pass BW (Hz) 8400 16800 33600 8400 16800 33600 8400 16800 33600 8400 16800 33600 Reset
PLL 30 ns over-equalization PLL 15 ns over-equalization PLL nominal equalization PLL 15 ns under-equalization PLL 30 ns under-equalization EBU data before concealment EBU data after concealment and fade EBU off - output LOW Level II clock accuracy (<1000 x 10-6) Level III clock accuracy (>1000 x Flags in EBU off Flags in EBU on double-speed mode single-speed mode 33.869 MHz crystal present 16.934 MHz crystal present standby 1: `CD-STOP' mode (note 1) standby 2: `CD-PAUSE' mode (note 1) operating mode off-track input at V1 no off-track input (V1 may be read via status) Kill-L at KILL output, Kill-R at V3 output V3 = 0; single Kill output V3 = 1; single Kill output Reset Reset Reset Reset Reset 10-6) Reset Reset Reset Reset
1998 Feb 16
13
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
REGISTER Versatile pins interface ADDRESS 1101 DATA 0000 XX01 XX10 XX11 01XX 10XX 11XX Note 1. Standby modes = CL, DA and RAB; normal operation. a) MISC, SCLK, WCLK, DATA, CL11 and DOBM; 3-state. b) CRIN, CROUT, CL16 and CLA; normal operation. c) V1, V2, V3, V4 and V5; normal operation. d) MOTO1 and MOTO2 - in standby 2 `CD-PAUSE'; normal operation. FUNCTION 4-line motor (using V4, V5) Q-to-W subcode at V4 V4 = 0 V4 = 1 de-emphasis signal at V5 V5 = 0 V5 = 1
SAA7345
INITIAL
Reset
Reset
e) MOTO1 and MOTO2 - in standby 1 `CD-STOP'; held LOW in PWM mode; 3-state in PDM mode. Error corrector The error corrector carries out t = 2, e = 0 error corrections on both C1 (32 symbol) and C2 (28 symbol) frames. Four symbols are used from each frame as parity symbols. The strategy t = 2, e = 0 means that the error corrector can correct two erroneous symbols per frame and detect all erroneous frames. The error corrector also contains a flag controller. Flags are assigned to symbols when the error corrector cannot ascertain if the symbols are definitely good. C1 generates output flags which are read (after de-interleaving) by C2, to help in the generation of C2 output flags. The C2 output flags are used by the interpolator for concealment of non-correctable errors. They are also output via the EBU signal (DOBM) and the MISC output with I2S for CD-ROM applications. The flags output pin CFLG provides information on the state of all error correction and concealment flags. Audio functions DE-EMPHASIS AND PHASE LINEARITY When de-emphasis is detected in the Q-channel subcode, the digital filter automatically includes a de-emphasis filter section. When de-emphasis is not required, a phase compensation filter section controls the phase linearity of the digital oversampling filter to 1 within the band 0 to 16 kHz. DIGITAL OVERSAMPLING FILTER The SAA7345 contains a 2 to 4 times oversampling filter. The filter specification of the 4 x oversampling filter is given in Table 2 and shown in Fig.12. These attenuations do not include the sample and hold at the DAC output or the DAC post filter. When using the oversampling filter, the output level is scaled -0.5 dB down, to avoid overflow on full-scale sinewave inputs (0 to 20 kHz).
1998 Feb 16
14
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
Table 3 Digital filter passband characteristics PASSBAND 0 to 19 kHz 19 to 20 kHz Table 4 Digital filter stopband characteristics. STOPBAND 24 kHz 24 to 27 kHz 27 to 35 kHz 35 to 64 kHz 64 to 68 kHz 68 kHz 69 to 88 kHz ATTENUATION 25 dB 38 dB 40 dB 50 dB 31 dB 35 dB 40 dB ATTENUATION 0.001 dB 0.03 dB
SAA7345
20 magnitude (dB) 0
MGA385
20
40
60 0 10 20 30 40 frequency (kHz) 50
Fig.12 Digital filter characteristics. CONCEALMENT A 1-sample linear interpolator becomes active if a single sample is flagged as erroneous but cannot be corrected. The erroneous sample is replaced by a level midway between the preceding and following samples. Left and right channels have independent interpolators. If more than one consecutive non-correctable sample is found, the last good sample is held. A 1-sample linear interpolation is then performed before the next good sample (see Fig.13).
1998 Feb 16
15
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
SAA7345
Interpolation
Hold
Interpolation
OK
Error
OK
Error
Error
Error
OK
OK
MGA372
Fig.13 Concealment mechanism.
MUTE, ATTENUATION AND FADE A digital level controller is present on the SAA7345 which performs the functions of soft mute, attenuation and fade.
Mute and Attenuation
Soft mute is activated by sending the Mute command to the fade control register (address 0000, data X000). The signal will reduced to zero in up to 128 steps (depending on the current position of the fade control), taking a maximum of 3 ms. Attenuation (-12 dB) is activated by sending the Attenuate command to the fade control register (data X01X). Attenuation and mute are cancelled by sending the Full Scale command to the fade control register (data X001). It will take 3 ms to ramp the output from mute to the full-scale level.
To control the fade counter in a continuous way, the step-up and step-down commands are available (fade control register data X101 and X100). They will increment or decrement the counter by 1 for each register write operation. * When issuing more than 1 step-up or step-down command in sequence, the write repeat mode may be used (see Fig.6). * A pause of at least 22 s is necessary between any two step-up or step-down commands. * When a step-up command is given when the fade counter is already at its full-scale value, the counter will not increment. DAC Interface The SAA7345 is compatible with a wide range of Digital-to-Analog Converters. Eleven formats are supported and are shown in Table 5. All formats are MSB first. fs is 44.1 kHz in single-speed mode and 88.2 kHz in double-speed mode.
Fade
The audio output level is determined by the value of the internal fade counter. counter Level = ---------------------- x maximum level 128 * The counter is preset to 128 by the Full Scale command if no oversampling is required. * The counter is preset to 120 (-0.5 dB scaling) by the Full Scale command if either 2fs or 4fs oversampling is programmed in the DAC output register (address 0011). * The counter is preset to 32 by the Attenuate command. * The counter is preset to 0 by the Mute command.
1998 Feb 16
16
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
Table 5 DAC interface formats MODE 1 2 3 4 5 6 7 8 9 10 11 Note 1. n = disc speed. 2. EIAJ is the abbreviation for: Electronic Industries Associated of Japan. DAC CONTROL REGISTER DATA 1010 1011 1110 0010 0110 000X 010X 110X 0011 0111 1111 SAMPLE FREQUENCY fs fs fs fs fs 4fs 4fs 4fs 2fs 2fs 2fs BITS 16 16 16 16 18 16 18 18 16 18 18 SCLK (MHz) 2.1168 x n(1) 2.1168 x 2.1168 x 2.1168 x 8.4672 x 8.4672 x n(1) n(1) n(1) n(1) n(1) FORMAT CD-ROM (I2S) CD-ROM Philips (EIAJ)(2) - 16 bits I2S
SAA7345
INTERPOLATION no no yes yes yes yes yes yes yes yes yes
2.1168 x n(1)
EIAJ - 16 bits EIAJ - 18 bits EIAJ - 16 bits EIAJ - 18 bits Philips I2S - 18 bits EIAJ - 16 bits EIAJ - 18 bits Philips I2S - 18 bits
8.4672 x n(1) 4.2336 x n(1) 4.2336 x n(1) 4.2336 x n(1)
1998 Feb 16
17
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Feb 16
SCLK DATA 0 15 LEFT CHANNEL DATA (WCLK NORMAL POLARITY) WCLK MISC CD-ROM MODE ONLY LSB VALID MSB VALID LSB VALID MSB VALID
MGA383
Philips Semiconductors
CMOS digital decoding IC with RAM for Compact Disc
0
15
Fig.14 Philips I2S data format (16-bit word length shown). 18
SCLK DATA 0 17 LEFT CHANNEL DATA WCLK MISC
MGA384
0
17
Product specification
SAA7345
Fig.15 EIAJ data format (18-bit word length shown).
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
EBU interface
SAA7345
The biphase-mark digital output signal at pin DOBM is in accordance with the format defined by the "IEC 958" specification. Three different modes can be selected via the EBU output control register (address 1010). Table 6 EBU output modes EBU CONTROL REGISTER DATA XX11 XX00 XX10 EBU OUTPUT AT DOBM PIN DOBM pin held LOW data taken before concealment, mute and fade data taken after concealment, mute and fade - HIGH if data is non-correctable (concealment flag) HIGH if data is non-correctable (concealment flag) EBU VALIDITY FLAG (BIT 28)
FORMAT The digital audio output consists of 32-bit words (subframes) transmitted in biphase-mark code (two transitions for a logic 1 and one transition for a logic 0). Words are transmitted in blocks of 384 (see Table 7). Table 7 EBU word format WORD Sync Auxiliary Error flags Audio sample Validity flag User data Channel status Parity bit SYNC The sync word is formed by violation of the biphase rule and therefore does not contain any data. Its length is equivalent to 4 data bits. The three different sync patterns indicate the following situations: * Sync B: - Start of a block (384 words), word contains left sample. * Sync M: - Word contains left sample (no block start). * Sync W: - Word contains right sample. BITS 0 to 3 4 to 7 4 8 to 27 28 29 30 31 - not used; normally zero CFLG error and interpolation flags when bit 3 of EBU control register is set to logic 1 first 4 bits not used (always zero) valid = logic 0 used for subcode data (Q-to-W) control bits and category code even parity for bits 4 to 30 AUDIO SAMPLE Left and right samples are transmitted alternately. VALIDITY FLAG Audio samples are flagged (bit 28 = logic 1) if an error has been detected but was non-correctable. This flag remains the same even if data is taken after concealment. USER DATA Subcode bits Q-to-W from the subcode section are transmitted via the user data bit. This data is asynchronous with the block rate. FUNCTION
1998 Feb 16
19
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
CHANNEL STATUS
SAA7345
The channel status bit is the same for left and right words. Therefore a block of 384 words contains 192 channel status bits. The category code is always CD. The bit assignment is shown in Table 8. Table 8 EBU channel status WORD Control BITS 0 to 3 FUNCTION copy of CRC checked Q-channel control bits 0 to 3; bit 2 is logic 1 when copy permitted; bit 3 is logic 1 when recording has pre-emphasis always zero CD: bit 8 = logic 1; all other bits = logic 0 set by EBU control register: 00 = Level II 01 = Level III
Reserved mode Category code Clock accuracy
4 to 7 8 to 15 28 to 29
Remaining KILL circuit
16 to 27 and 30 to 191 always zero Several output modes are supported: 1. Pulse Density, 2-line (true complement output), 1 MHz sample frequency. 2. PWM output, 2-line, 22.05 kHz modulation frequency. 3. PWM-output, 4-line, 22.05 kHz modulation frequency. 4. CDV motor mode. The modes are selected via the motor output configuration register (address 0110). PULSE DENSITY MODE In the Pulse Density mode the motor output pin MOTO1 is the pulse density modulated motor output signal. A 50% duty cycle corresponds with the motor not actuated, higher duty cycles mean acceleration, lower mean braking. In this mode, the MOTO2 signal is the inverse of the MOTO1 signal. Both signals change state only on the edges of a 1 MHz internal clock signal. Possible application diagrams are shown in Fig.16.
The KILL circuit detects digital silence by testing for an all-zero or all-ones data word in the left or right channel before the digital filter. The output is switched active LOW when silence has been detected for at least 200 ms. Two modes are available, selected by the versatile pins register (address 1100): 1-PIN KILL MODE Active LOW signal on KILL pin when digital silence has been detected on both LEFT and RIGHT channels for 200 ms. 2-PIN KILL MODE Independent digital silence detection for left and right channels. The KILL pin is active LOW when digital silence has been detected in the LEFT channel for 200 ms, and V3 is active LOW when digital silence has been detected in the RIGHT channel for 200 ms. When MUTE is active then the KILL output is forced LOW. Spindle motor control The spindle motor speed is controlled by a fully integrated digital servo. Address information from the internal 8 frame FIFO and disc speed information are used to calculate the motor control output signals.
1998 Feb 16
20
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
22 k MOTO1 10 nF VSS 22 k
SAA7345
+ -
M
+ -
VSS
MOTO2 10 nF
VDD 22 k
22 k MOTO1 22 k VSS 10 nF VSS
+ -
22 k 22 k
M
VSS
V DD
MGA363 - 1
Fig.16 Motor pulse density application diagrams.
PWM MODE, 2-LINE In the PWM mode the motor acceleration signal is put in pulse-width modulation form on the MOTO1 output and the motor braking signal is pulse-width modulated on the MOTO2 output. Figure 17 shows the timing and Fig.18 a typical application diagram.
t rep = 45 s MOTO1 MOTO2
t dead
240 ns
Accelerate
Brake
MGA366
Fig.17 Motor 2-line PWM mode timing.
+
M 10 100 nF
MOTO1
MOTO2
VSS
MGA365 - 2
Fig.18 Motor 2-line PWM mode application diagram.
1998 Feb 16
21
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
PWM MODE, 4-LINE
SAA7345
Using two extra outputs from the Versatile Pins Interface, it is possible to use the SAA7345 with a 4-input motor bridge. Figure 19 shows the timing and Fig.20 a typical application diagram.
t rep = 45 s MOTO1 MOTO2 V4 V5
t dead
240 ns
t ovl = 240 ns
MGA367 - 1
Accelerate
Brake
Fig.19 Motor 4-line PWM mode timing.
+
V4
V5
M 10 100 nF
MOTO1
MOTO2
VSS
MGA364 - 2
Fig.20 Motor 4-line PWM mode application diagram. CDV MODE In the CDV motor mode, the FIFO position will be put in pulse-width modulated form on the MOTO1 pin (carrier frequency 300 Hz) and the PLL frequency signal will be put in pulse-density modulated form on the MOTO2 pin (carrier frequency 4.23 MHz). The integrated motor servo is disabled in this mode. Remark: The PWM signal on MOTO1 corresponds to a total memory space of 20 frames, therefore the nominal FIFO position (half-full) will result in a PWM output of 60%.
1998 Feb 16
22
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
OPERATION MODES
SAA7345
The motor servo has the operation modes as shown in Table 9 and is controlled by the motor mode register (address 0001). Table 9 Operation modes. MODE Start mode 1 Start mode 2 DESCRIPTION Disc is accelerated by applying a positive voltage to the spindle motor. No decisions are involved and the PLL is reset. No disc speed information is available for the microcontroller. The disc is accelerated as in Start mode 1, however the PLL will monitor the disc speed. When the disc reaches 75% of its nominal speed, the controller will switch to Jump mode. The motor status signals are valid (register 0010). Motor servo enabled but FIFO kept reset at 50%. The audio is muted but it is possible to read the subcode. Similar to Jump mode but motor integrator is kept at zero. Used for long jumps. FIFO released after resetting to 50%. Audio mute released. Disc is braked by applying a negative voltage to the motor. No decisions are involved. The disc is braked as in Stop mode 1, but the PLL will monitor the disc speed. As soon as the disc reaches 12% of its nominal speed, the MOTSTOP status signal will go HIGH and switch the motor servo to off mode. Motor not steered. FIFO OVERFLOW If FIFO overflow occurs during Play mode (e.g. as a result of motor shock), the FIFO will be automatically reset to 50% and the audio interpolator is activated to minimize the effect of data loss.
Jump mode Jump mode 1 Play mode Stop mode 1 Stop mode 2
Off mode POWER LIMIT
In Start mode 1, Start mode 2, Stop mode 1 and Stop mode 2, a fixed positive or negative voltage is applied to the motor. This voltage can be programmed as a percentage of the maximum possible voltage via the motor output configuration register (address 0110) to limit current drain during start and stop. The following power limits are possible: * 100% of maximum (no power limit) * 75% of maximum * 50% of maximum * 37% of maximum. LOOP CHARACTERISTICS The gain and cross-over frequencies of the motor control loop can be programmed via the motor gain and bandwidth registers (addresses 0100 and 0101). The possible parameter values are as follows: Gain: 3.2, 4.0, 6.4, 8.0 12.8, 16, 26.6 or 32. Cross-over frequency, f4: -0.5, -0.7, -1.4 or -2.8 Hz. Cross-over frequency, f3: -0.85, -1.71 or -3.42 Hz.
1998 Feb 16
23
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
SAA7345
MGA362 - 2
G
f4
f3
BW
f
Fig.21 Motor servo mode diagram.
Versatile pins interface The SAA7345 has five pins that can be reconfigured for different applications as shown in Table 10. Table 10 Versatile pins SYMBOL V1 PIN 3 TYPE input CONTROL REGISTER ADDRESS 1100 CONTROL REGISTER DATA XXX1 XXX0 V2 V3 4 26 input output - 1100 - XX0X X01X X11X V4 25 output 1101 0000 XX01 XX10 XX11 V5 24 output 1101 01XX 10XX 11XX FUNCTION off-track input (from digital servo) input may be read via status register (address 0010 data X101) input may be read via status register (address 0010 data X110) kill output for right channel output = logic 0 output = logic 1 4-line motor drive (using V4 and V5) Q-to-W subcode output output = logic 0 output = logic 1 de-emphasis output (active HIGH) output = logic 0 output = logic 1
1998 Feb 16
24
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
Flags Output (CFLG) (open drain output)
SAA7345
A 1-bit flag signal is available at the CFLG pin. This signal shows the status of the error corrector and interpolator and is updated every frame (7.35 kHz).
handbook, full pagewidth
11.3 s CFLG F1 F2 F3 F4 F5 F6 F7
45.4 s F1
MGA370
Fig.22 Flags output timing.
Table 11 Meaning of flag bits. F1 0 1 X X X X X X X X X X X X F2 X X 0 0 1 1 X X X X X X X X F3 X X 0 1 0 1 X X X X X X X X F4 X X X X X X 0 0 1 1 X X X X F5 X X X X X X 0 1 0 1 X X X X F6 X X X X X X X X X X 0 0 1 1 F7 X X X X X X X X X X 0 1 0 1 no absolute time sync absolute time sync C1 frame contained no errors C1 frame contained 1 error C1 frame contained 2 errors C1 frame non-correctable C2 frame contained no errors C2 frame contained 1 error C2 frame contained 2 errors C2 frame non-correctable no interpolations at least one 1-sample interpolation at least one hold and no interpolations at least one hold and one 1-sample interpolation Double speed mode Double speed mode is programmed via the Speed control register (address 1011). It is possible to program double speed independent of clock frequency, but optimum performance is achieved with a 33.8688 MHz crystal or a ceramic resonator. MEANING
ABSOLUTE TIME SYNC The first flag bit (F1) is the absolute time sync signal. It is the FIFO-passed subcode-sync and relates the position of the subcode-sync to the audio data (DAC output). The flag may be used for special purposes such as synchronization of different players. FLAGS AT EBU OUTPUT The CFLG flags are available on bit 4 of the EBU data format when bit 3 of the EBU output control register (address 1010) is set to logic 1.
1998 Feb 16
25
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI(max) VO IO Tamb Tstg Ves1 Ves2 Notes 1. All VDD and VSS connections must be made externally to the same power supply. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor with a rise time of 15 ns. 3. Equivalent to discharging a 200 pF capacitor via a 2.5 H series inductor. CHARACTERISTICS VDD = 3.4 to 5.5 V; VSS = 0 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Supply VDD IDD supply voltage supply current VDD = 5 V 3.4 - 5.0 22 - - - 1.0 - - - - 5.5 50 PARAMETER CONDITIONS MIN. TYP. supply voltage maximum input voltage output voltage output current (continuous) operating ambient temperature storage temperature electrostatic handling electrostatic handling note 2 note 3 PARAMETER CONDITIONS note 1 MIN. -0.5 -0.5 -0.5 - -40 -55 -2000 -200
SAA7345
MAX. +6.5 +6.5 20 +85 +125 +2000 +200 V V VDD + 0.5 V
UNIT
mA C C V V
MAX.
UNIT
V mA
Analog Front End (VDD = 4.5 to 5.5 V); comparator inputs HFIN and HFREF fclk Vth clock frequency switching thresholds 8 1.2 35 VDD - 0.4 MHz V
Analog Front End (VDD = 3.4 to 5.5 V); comparator inputs HFIN and HFREF fclk Vtpt VIL VIH ILI CI clock frequency HFIN input voltage level 8 - -0.3 0.7VDD VI = 0 to VDD -10 - 20 - MHz V
Digital inputs CL and RAB LOW level input voltage HIGH level input voltage input leakage current input capacitance 0.3VDD +10 10 V A pF VDD + 0.3 V
1998 Feb 16
26
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
SYMBOL PARAMETER CONDITIONS - 0.2VDD - VI = 0 V PORE only - - 1 MIN. - - 0.33VDD 50 - - - - - - - - - - - - - - - - - - - - - - TYP.
SAA7345
MAX.
UNIT
Digital inputs PORE, V1 and V2 Vthr Vthf Vhys RPU CI trw VOL VOH CL tr tf VOL switching threshold voltage rising switching threshold voltage falling hysteresis voltage input pull-up resistance input capacitance reset pulse width 0.8VDD - - - 10 - V V V k pF s
Digital outputs CL16 and CLA LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time CL = 20 pF; note 1 CL = 20 pF; note 1 VDD = 4.5 to 5.5 V; IOL = 10 mA VDD = 3.4 to 5.5 V; IOL = 5 mA VOH HIGH level output voltage VDD = 4.5 to 5.5 V; IOH = -10 mA VDD = 3.4 V to 5.5 V; IOH = -5 mA CL tr tf VOL IOL CL tf VOL IOL CL tf load capacitance output rise time output fall time CL = 20 pF; note 1 CL = 20 pF; note 1 IOL = 1 mA IOL = 1 mA IOH = -1 mA 0 VDD - 0.4 - - - 0.4 VDD 50 15 15 V V pF ns ns
Digital outputs V4 and V5 LOW level output voltage 0 0 VDD - 1 VDD - 1 - - - 1.0 1.0 VDD VDD 50 15 15 V V V V pF ns ns
Open-drain output CFLG LOW level output voltage LOW level output current load capacitance output fall time CL = 20 pF; note 1 IOL = 1 mA 0 - - - 0.4 2 50 30 V mA pF ns
Open-drain outputs KILL and V3 LOW level output voltage LOW level output current load capacitance output fall time CL = 20 pF; note 1 0 - - - 0.4 2 50 15 V mA pF ns
1998 Feb 16
27
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
SYMBOL PARAMETER CONDITIONS MIN. - - - - - - - - - - - - - - - - - - - - - - - TYP.
SAA7345
MAX.
UNIT
3-state outputs MISC, SCLK, WCLK, DATA and CL11 VOL VOH CL tr tf ILI VOL LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time 3-state leakage current CL = 20 pF; note 1 CL = 20 pF; note 1 VI = 0 to VDD VDD = 4.5 to 5.5 V; IOL = 10 mA VDD = 3.4 to 5.5 V; IOL = 5 mA VOH HIGH level output voltage VDD = 4.5 to 5.5 V; IOH = -10 mA VDD = 3.4 to 5.5 V; IOH = -5 mA CL tr tf ILI VIL VIH ILI CI VOL VOH CL tr tf gm RO CI ILI fxtal Cfb CO load capacitance output rise time output fall time 3-state leakage current CL = 20 pF; note 1 CL = 20 pF; note 1 VI = 0 to VDD IOL = 1 mA IOH = -1 mA 0 VDD - 0.4 - - - -10 0.4 VDD 50 15 15 +10 V V pF ns ns A
3-state outputs MOTO1, MOTO2 and DOBM LOW level output voltage 0 0 VDD - 1 VDD - 1 - - - -10 -0.3 0.7VDD VI = 0 to VDD IOL = 1 mA IOH = -1 mA CL = 20 pF; note 1 CL = 20 pF; note 1 -10 - 0 VDD - 0.4 - - - - - - -10 1.0 1.0 VDD VDD 50 10 10 +10 V V V V pF ns ns A
Digital input/output DA LOW level input voltage HIGH level input voltage 3-state leakage current input capacitance LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time 0.3VDD +10 10 0.4 VDD 50 15 15 - - 10 +10 V A pF V V pF ns ns VDD + 0.3 V
Crystal oscillator input CRIN (external clock) mutual conductance at start-up output resistance at start-up input capacitance input leakage current 4 11 - - mS k pF A
Crystal oscillator output CROUT (see Fig.26) crystal frequency feedback capacitance output capacitance 8 - - 16.9344 - - 35 5 10 MHz pF pF
1998 Feb 16
28
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
SYMBOL I2S timing CLOCK OUTPUT SCLK (see Fig.23) tcy output clock period sample rate = fs sample rate = 2fs sample rate = 4fs tH clock HIGH time sample rate = fs sample rate = 2fs sample rate = 4fs tL clock LOW time sample rate = fs sample rate = 2fs sample rate = 4fs tsu set-up time sample rate = fs sample rate = 2fs sample rate = 4fs th hold time sample rate = fs sample rate = 2fs sample rate = 4fs I2S timing (double speed) CLOCK OUTPUT SCLK (see Fig.23) tcy output clock period sample rate = fs sample rate = 2fs sample rate = 4fs tH clock HIGH time sample rate = fs sample rate = 2fs sample rate = 4fs tL clock LOW time sample rate = fs sample rate = 2fs sample rate = 4fs tsu set-up time sample rate = fs sample rate = 2fs sample rate = 4fs th hold time sample rate = fs sample rate = 2fs sample rate = 4fs - - - 83 42 21 83 42 21 48 24 12 48 24 12 236.2 118.1 59.1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 166 83 42 166 83 42 95 48 24 95 48 24 472.4 236.2 118.1 - - - - - - - - - - - - - - - - - - - - - - - - - - - PARAMETER CONDITIONS MIN. TYP.
SAA7345
MAX.
UNIT
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1998 Feb 16
29
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
SYMBOL PARAMETER CONDITIONS MIN. TYP.
SAA7345
MAX.
UNIT
Microcontroller interface timing (see Figs 24 and 25) INPUTS CL AND RAB tL tH tr tf READ MODE tdRD tdRZ tpd delay time RAB to DA valid delay time RAB to DA high-impedance propagation delay CL to DA single speed double speed WRITE MODE tsuD thD tsuCR tdWZ Notes 1. Timing reference voltage levels are 0.8 V and VDD - 0.8 V. 2. Negative set-up time means that data may change after clock transition. set-up time DA to CL hold time CL to DA set-up time CL to RAB delay time DA high-impedance to RAB single speed; note 2 double speed; note 2 single speed double speed single speed double speed -700 -340 - - 260 140 50 - - - - - - - - - 980 500 - - - ns ns ns ns ns ns ns 0 0 700 340 - - - - 50 50 980 500 ns ns ns ns input LOW time input HIGH time rise time fall time single speed double speed single speed double speed single speed double speed 500 260 500 260 - - - - - - - - - - - - 480 240 ns ns ns ns ns ns
clock period t cy tL tH V DD - 0.8 V SCLK 0.8 V th WCLK DATA MISC t su V DD - 0.8 V 0.8 V
MGA376 - 1
Fig.23 I2S timing.
1998 Feb 16
30
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
SAA7345
tr
tf V DD - 0.8 V
RAB tr t f tH V DD - 0.8 V 0.8 V t pd DA (SAA7345) high impedance tL V DD - 0.8 V 0.8 V
MGA377 - 1
0.8 V
CL
t dRD
t dRZ
Fig.24 Microcontroller timing; READ mode.
tr t RAB suCR
tH
tf V DD - 0.8 V
0.8 V t f tH tr VDD - 0.8 V CL 0.8 V t suD DA (microcontroller) tL t hD t dWZ tL
V
DD
- 0.8 V high impedance
MGA378 - 1
0.8 V
Fig.25 Microcontroller timing; WRITE mode.
1998 Feb 16
31
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
APPLICATION INFORMATION
SAA7345
CRIN 33.8688 MHz (3rd overtone) CRYSTAL 100 k CROUT 1 nF 10 pF 10 pF 2.2 k VDDA VSSA
3.3 H
CRIN 16.9344 MHz CRYSTAL 100 k CROUT 33 pF 33 pF 2.2 k VDDA VSSA
CRIN 33.8688 CERAMIC GENERATOR 100 k CROUT 5 pF 5 pF 2.2 k VDDA VSSA
MGA360 - 1
Fig.26 Application circuits for crystal oscillator.
1998 Feb 16
32
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
SAA7345
V R6 2.2 C12 4.7 F (63 V) VDD
1 to DOBM transformer 2 3 4 5 6 7 8 R2 22 k C2 47 pF 9 10 11 C4 100 nF C3 22 nF V R4 2.2 C6 4.7 F (63 V)
(1)
VDD2 CL11 DOBM V1 V2 TEST2 TEST1 ISLICE HFIN HFREF IREF
V SS2
11 MHz clock output
X8
C13 100 nF
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 MOTOR INTERFACE microcontroller interface
CFLG RAB CL DA CLA
SAA7345
PORE KILL V3 V4 V5
CROUT
V SS1
DATA
X6 HFIN
MISC
SCLK
CRIN
CL16
R3 2.2 k C1 2.2 nF
V DDA VSSA
WCLK
V DD1
MOTO2 MOTO1
12 13 14 15 16 17 18 19 20 21 22 VDD
C7 100 nF
C11 100 nF
to DAC
X9
16 MHz clock output
(2)
MGA375 - 1
(1) Diagram is for a 5 V application. For 3.4 V applications an additional resistor of 150 k should be added between IREF (pin 10) and ground. (2) For crystal oscillator circuit see Fig.26.
Fig.27 Typical SAA7345 application diagram.
1998 Feb 16
33
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm
SAA7345
SOT205-1
c
y X
33 34
23 22 ZE
A
e E HE wM bp pin 1 index 44 1 11 ZD bp D HD wM B vM B 12 detail X L Lp A A2 A1 (A 3)
e
vM A
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.60 A1 0.25 0.05 A2 2.3 2.1 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 14.1 13.9 E (1) 14.1 13.9 e 1 HD 19.2 18.2 HE 19.2 18.2 L 2.35 Lp 2.0 1.2 v 0.3 w 0.15 y 0.1 Z D (1) Z E (1) 2.4 1.8 2.4 1.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT205-1 REFERENCES IEC 133E01A JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
1998 Feb 16
34
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm.
SAA7345
If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1998 Feb 16
35
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7345
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1998 Feb 16
36
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
NOTES
SAA7345
1998 Feb 16
37
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
NOTES
SAA7345
1998 Feb 16
38
Philips Semiconductors
Product specification
CMOS digital decoding IC with RAM for Compact Disc
NOTES
SAA7345
1998 Feb 16
39
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
Internet: http://www.semiconductors.philips.com
SCA57
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545102/00/05/pp40
Date of release: 1998 Feb 16
Document order number:
9397 750 03314

▲Up To Search▲

Price & Availability of SAA7345GP

	To Download SAA7345GP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .